1. Field of the Invention
The present invention relates to a break address detecting circuit, and more particularly to a break addressing detecting circuit for setting a breakpoint in debugging a program for a microprocessor, a signal processor, or the like.
2. Description of the Prior Art
In the development of a program for a microprocessor, a signal processor, or the like, it is customary to temporarily halt, i.e., break, the execution of the program run by the processor at a certain program address and read the internal status of the processor, or execute the program one instruction at a time and follow the transition of the internal status of the processor each time an instruction is executed (step-by-step operation).
Heretofore, in order to break the execution of a program or execute a program step by step, an address where a program break is to occur is compared with actual addresses of the program which is run by a processor, and the operation of the processor is interrupted when the compared addresses agree with each other. FIG. 1 of the accompanying drawings shows a conventional break address detecting circuit for breaking the execution of a program.
As shown in FIG. 1, the conventional break address detecting circuit has a register 1 for holding and outputting a stop address ADstp where the operation of a processor is to be halted, and a comparator 2 for outputting a break signal BRK when an address ADpro of a program that is run by the processor (hereinafter referred to as a "program address ADpro") is compared and agrees with the output signal from the register 1, i.e., the stop address ADstp.
To debug a program using the conventional break address detecting circuit, an address where a program break is to occur is transferred to the register 1. Then, the processor is reset to start the program. The processor successively executes instructions in the sequence according to the program. At this time, program addresses that are successively executed by the processor are addresses in a program memory from which the program is read. The program addresses ADpro are successively inputted to the comparator 2. The comparator 2 compares the stop address ADstp held in the register with the program addresses ADpro. When the stop address ADstp agrees with one of the program addresses ADpro, the comparator 2 outputs a break signal BRK of an active level, breaking the operation of the processor.
The step-by-step operation is essentially the same as the above breaking operation. According to the step-by-step operation, an address of the program which is to be executed next to the address where the program is halted is stored in the register 1, and the processor is reset from the broken condition to execute the program from the start. Alternatively, the break is canceled and an instruction line next to the break is executed, whereupon the execution of the program is interrupted again. To repeat the step-by-step operation, the above process is repeated a desired number of times.
However, the conventional break address detecting circuit suffers the following drawbacks:
Since a breakpoint is indicated by a program address, if a program contains a branch instruction to cause execution to jump to a later address or a loop instruction to repeat the same instruction a plurality of times, then when a break is to occur at an instruction line that is to be executed a plurality of times, the program is halted when the instruction is executed for the first time, and it is impossible to break the program after the loop instruction is executed a desired number of times.
In decoding instructions according to the step-by-step operation, if the instructions contain a branch instruction, then it is necessary to know in advance whether execution is branched from the branch instruction. Therefore, a controller for controlling the debugging process needs a processor simulator.
If a break of a program is to occur after elapse of a certain period of time from the execution of an instruction, i.e., after the instruction at a certain step is executed, then in the event that the program contains a branch instruction, an execution address at the time the step is executed can only be determined by carrying out the step-by-step operation successively and counting the steps. Such a process is complex and the execution time is very long.